Two Clocks From One Master Through Separate Ports

• If a PLL generated the two clocks, their frequency and period will be the same.
• In the constraints both clocks are generated from different ports, so the tool sees them as different clocks until you provide a balancing relationship through SDC constraints, even though they are actually synchronous.
• The problem arises with balancing: if the launch flop uses clka, the capture flop uses clkb, and a data path runs between them, timing violations appear because of how balancing and clock building are done.
• You must specify balancing options between the two clocks even though their period is the same.

KEY The tool treats port-defined clka/clkb as asynchronous until SDC balancing constraints relate them as synchronous.

Why Clock Gating Is Timing-Critical

Clock-gating cells usually have very large fanouts, which produce large latencies from the clock-gate output to the clock sinks. This causes timing failures both on the enable pin going into the clock gate and on the paths after the clock-gate output.

KEY Large clock-gate fanout creates big latencies, stressing both the enable-pin path and post-gate paths.

Ideal Timing-Path Equations

Basic STA relations: Clock period > Tcq + Tpd + Tsu, where Tcq is max clock-to-output, Tpd is max logic propagation delay, and Tsu is max setup time.

Hold time < Tmin(register) + Tmin(logic). With skew: clock period + skew > Tcq + Tpd + Tsu, and hold + skew < Tcq + Tpd + Tmin(logic).

With jitter: clock period - worst-case jitter > Tcq + Tpd + Tsu, and hold + worst-case jitter < Tmin(R) + Tmin(logic), where worst-case jitter = 2 x jitter. Max operating frequency therefore depends on Tcq, Tpd and Tsu. Setup violations can be eased by frequency or temperature; hold