violations cannot be fixed by frequency.

KEY Clock period must exceed Tcq + Tpd + Tsu; skew and jitter tighten the inequality.

Clock Skew - Positive, Negative, Zero

Clock skew is when the clock, though from one source, arrives at different elements at different times - caused by temperature variation, decoupling, interconnect length or material imperfections.

Positive skew: the source (launch) flop gets the clock before the capture flop - this helps operating frequency but makes hold harder. Negative skew: the source gets the clock after the capture flop - this lowers operating frequency. Zero skew: clock arrives in sync at both. Clock skew is also called clock uncertainty.

KEY Skew = clock arriving at different times; positive helps setup/hurts hold, negative hurts frequency.

Clock Jitter

Clock jitter is the deviation of a clock edge from its ideal position, caused by noise, power-supply variation, or interference from neighbouring circuits.

Jitter makes the clock effectively faster or slower, which can violate setup or hold constraints and degrade the chip's performance or functionality, so it is an important parameter in timing analysis.