at a gate input takes finite time to reach the output.

• Gate delay is a function of the input transition time and the load (Cnet + Cpin); cell delay means the same thing as gate delay. Source delay (source latency):
• The delay from the clock origin point to the clock definition point, that is from the clock source to the beginning of the clock tree. Network delay (latency):
• Also called insertion delay, it is the delay from the clock definition point to the clock pin of the register. Insertion delay:
• The delay from the clock definition point to a register's clock pin. Transition delay (slew):
• The time taken for a signal to change state - to rise from logic 0 to logic 1 or fall from logic 1 to logic 0, usually measured between the 10%-90% or 20%-80% points.
• Slew is the rate of change of logic level, measured in volts per nanosecond. Rise time:
• The time between the signal crossing a low threshold and crossing a high threshold; thresholds may be absolute or percentages (10%/90% or 20%/80%) of the voltage swing. Fall time:
• The time between the signal crossing a high threshold and crossing a low threshold, with thresholds defined the same way as for rise time. Path delay:
• Also called pin-to-pin delay - the delay from a cell's input pin to its output pin. Net delay (wire delay):
• The difference between when a signal is applied to a net and when it reaches the other devices on that net, caused by the net's resistance and capacitance; net delay is a function of Rnet and Cnet+Cpin. Propagation delay:
• Measured between the 50% point of the input transition and the