Chapter 10

Devices, Variation & Low-Power

Power Saving with HVT and LVT Cells

Use HVT cells on paths with positive slack - they are slower but leak less, and unused positive slack only wastes power.
Use LVT cells on paths with negative slack - they are fast but very leaky, so limit them to timing-critical paths only.

The goal is to give back surplus slack with HVT cells and save leakage power, while spending LVT cells only where timing demands it.

KEY HVT on relaxed paths to cut leakage; LVT only where timing is tight.

With zero skew every flop is clocked at exactly the same instant, which concentrates switching activity and increases power consumption.

KEY Zero skew triggers all flops simultaneously, raising peak power consumption.

As process (P) increases, delay increases; delay generally varies with process, voltage and temperature.

KEY Delay rises with increasing process value, and varies with voltage and temperature too.

Header switch (PMOS) characteristics:

Higher resistance due to lower mobility, so the slew/transition is slower, meaning slower switching activity.
More short-circuit power because of the higher transition time.
Lower leakage power thanks to the higher resistance - an advantage.
Switch-on and switch-off take longer because of the higher