KEY Use the get*Mode commands - getEcoMode, getTrialRouteMode, getDetailRouteMode and so on.

Unate Arcs and the DFF

Positive unate: a timing arc is positive unate if the output transitions in the same direction as the input, or does not change. Examples are AND and OR gates.

Negative unate: a timing arc is negative unate if the output transitions opposite to the input, or does not change. Examples are NAND, NOR and inverter.

Non-unate: in a non-unate arc the output direction cannot be determined from a single input's transition alone - it also depends on the state of the other inputs. An XOR gate is an example.

Unateness is defined for every timing arc of every cell in the library. A DFF's CP-to-Q arc is non-unate because the output edge depends not only on the clock transition but also on the value on the D pin. In the lib this appears as a timing group on pin Q with related_pin CP, timing_sense non_unate, and timing_type rising_edge.

KEY Positive unate keeps direction (AND/OR), negative unate inverts it (NAND/inverter), non-unate depends on other inputs (XOR); a DFF's CP-to-Q arc is non-unate.

Negative Library Values

• A library hold margin can be negative. A negative hold check means the data pin can change slightly before the clock pin and still satisfy the hold requirement.
• A library setup margin can also be negative. This means the data can change slightly after the clock pin and still meet the setup check.
• Can both setup and hold be negative at once? No. For the checks to be consistent, the sum of setup and hold must be positive - so if one is negative, the other must be positive enough to keep the total positive.
• A negative hold time on scan data input pins is helpful: it gives