boundaries into the block. Inside the block the clock is distributed through a fixed number of stages via a mesh of clock buffers, which should be symmetric.

KEY The clock grid uses staged, symmetric buffer meshes to give uniform source-to-sink delay.

Clock Mesh Distribution System

In a clock mesh the main clock is split into parallel paths by drivers, and an array of buffers is cross-connected in a metallic mesh. The drivers feed these buffers, which route to the clock sinks.

The mesh cross-links create a resonant structure that cancels buffer delay. It is used in high-speed microprocessors, with clock routes usually shielded to limit coupling. Because the mesh tolerates variation well, clock skew is greatly reduced.

KEY A clock mesh cross-connects buffers into a resonant grid - low skew, used in high-speed CPUs.

Clock Tree Distribution System

In a clock tree the clock is distributed to all receivers (flip-flops, counters, etc.) through an optimal number of stages. The stage count need not be equal everywhere, and because there are fewer stages, power dissipation is low.

The clock tree distribution system is best suited to slow-clock designs.

KEY A clock tree distributes the clock through few, optimal stages - low power, best for slow clocks.

Clock Mesh vs Clock Tree

Clock mesh:

A mesh net smooths the arrival-time differences from multiple mesh drivers.
Mesh drivers connect to the mesh net as a multi-driven net.
Gives much lower clock skew and insertion delay, but has more design stages.
Higher power dissipation, harder to implement, and needs more routing