Effects of Metastability

• With high fan-out the circuit can go metastable and the flip-flop toggles unintentionally, giving unexpected system behaviour.
• The circuit draws excessive current.
• The output behaves non-deterministically.
• The output of a clocked pass gate does not charge properly.
• The circuit fails to meet its timing constraints.

KEY Metastability causes unintended toggling, excess current, non-deterministic output and timing failures.

Clock Jitter and Its Sources

Clock jitter is the inaccuracy of the clock edge introduced by the clock-generation circuitry relative to an ideal clock - it can be seen as a statistical variation in the clock period or duty cycle.

Sources include temporal power-supply variation (changing activity shifts the supply seen by global or regional clock buffers), PLL jitter (supply variation at the PLL, non-zero component response time, reference-clock jitter multiplied by the PLL, and supply noise on the global clock distribution affecting the feedback clock), wire coupling (changing data alters coupling cycle to cycle), and dynamic de-skewing circuitry.

KEY Jitter = clock-edge inaccuracy from supply variation, PLL noise, wire coupling and de-skew circuitry.