KEY No - GRC size is tool-computed dynamically, defaulting to the standard-cell row height, with no user control.

Retention Flop Secondary-Pin Routing

A secondary power stripe runs between the primary power stripes throughout the design. During placement, make sure all retention flops are aligned to the secondary power stripes to keep the resistance of their secondary power connections low. Apply a route-as-signal attribute to the secondary power pins of the retention flops, then apply a 3x-width NDR on those signal-routed power nets. These nets should be routed before the clock nets and signal nets.

KEY Align retention flops to secondary power stripes, route their secondary pins as signal with a 3x-width NDR, ahead of clock and signal nets.

Antenna Violations on Signal vs Power Nets

Power nets do not connect directly to transistor gates, so they do not accumulate the gate charge that causes antenna damage; signal nets do route to gate inputs and are therefore vulnerable.

KEY Antenna violations need a gate connection - power nets don't tie to gates, signal nets do.

Pre-Route to Post-Route Correlation

• Pre-route, interconnect RC delay is computed with the Elmore delay engine by default in ICC Compiler, while post-route uses the Arnoldi engine. Check which engine is in use pre-route, and switch to the AWE (Asymptotic Waveform Evaluation) engine pre-route for better correlation with post-route.
• Pre-route ignores coupling caps, so crosstalk is absent there, while post-route includes crosstalk - creating a correlation gap. Report the same path at the route and post-CTS stages; if crosstalk is the culprit, reducing congestion will improve correlation.
• Raising the uncertainty value at post-CTS and re-running post-CTS optimization can improve correlation, but it over-optimizes