• Examine the skew - excessive skew can be improved during CTS.
• Check the setup time and clk-to-Q access time of the flop or memory.

KEY Check clock validity/skew, then data-path cell strength, congestion detours, delta-derate, skew and flop timing arcs.

Spacing for Thick Metal Layers

Thick metal layers are more prone to manufacturing variation, so they require additional spacing.

KEY Thick metal layers vary more in manufacturing, so they need extra spacing.

Routing Blockage at the Die Edge

• It stops the tool from routing wires outside the die area.
• It keeps routes well inside the design, avoiding DRC violations at the die boundary.

KEY A die-edge routing blockage keeps routes inside the die and prevents boundary DRCs.

Fixing Hold Violations After Routing

• Add buffers or delay cells on the violating paths.
• Enable the appropriate view and run route_opt -hold.

KEY Fix post-route hold by adding buffers and running route_opt -hold on the right view.

Metal Layer Allocation

Top layers: used for power, since they can carry more current. Middle layers: used for the clock network. Bottom layers: used for the uniform distribution of power down to the standard cells.

KEY Top metals carry power, middle metals carry the clock, bottom metals distribute power to cells.