KEY A net's metal layer can be changed by attribute, by NDR, or manually.
DFM and Single Vias at Lower Nodes
- High-toggle cells must be identified - clock nets at 200 percent and signal nets from VCD, TCF or SAIF.
- Clustering of clock cells becomes a bigger concern.
KEY At lower nodes, identifying high-toggle cells and clustered clock cells becomes more important for DFM.
The Problem With Metal Fill
- Dummy metal fill adds extra coupling capacitance.
- It has a stronger effect at lower technology nodes, hurting performance.
- Dummy metal fill generally has a larger minimum-spacing rule defined for it.
- A route blockage is not a layer number defined in the GDS.
- A special layer called EXCLUDE is defined to block metal fill; it increases the spacing between metal layers, and with the same amount of metal the coupling capacitance falls because of the larger spacing.
KEY Metal fill adds coupling capacitance, worse at low nodes - the EXCLUDE layer enforces spacing to cut it.
DFM With a Perfect Foundry
DFM contains two kinds of rules: recommended rules and violation rules.
KEY DFM still matters because it covers both recommended rules and violation rules.
Delay of 1X vs 2X Width Metal
Width is inversely proportional to resistance, so widening a wire lowers its R; at the same time a wider wire has higher capacitance. Since delay depends on the RC product, the delay can increase or decrease