The Dishing Effect Dishing is the height difference between the oxide in the spaces and the metal in the trenches. It is caused by chemical mechanical planarization (CMP) and can be reduced effectively with dummy-fill techniques. KEY Dishing is a CMP-induced metal-vs-oxide height difference, reduced by dummy fill.

Violations Resolved in LVS

• Shorts.
• Opens.
• Missing text layers.
• Missing library cells in the GDS.
• Missing soft layers. KEY LVS catches shorts, opens, and missing text/library/soft layers.

Multi-Driven Nets A multi-driven net is created in RTL by attaching multiple drivers - of the same or different strengths - to one net. This is considered bad practice: driver strength can be heavily altered by manufacturing defects, leading to post-silicon verification failures. Many EDA tools do not allow multi-driven nets, and designers are expected to remove all of them from the design. KEY Multi-driven nets have several drivers on one net - bad practice, EDA tools require them removed.

DRV vs DRC Both judge chip quality at different stages of the PD flow. DRC ensures the layout obeys the foundry's predefined technology rules for manufacturability - checked at every stage after placement, and the count should be very low post-route. Typical DRCs: shorts, opens, metal/well spacing, minimum length, area and enclosure. DRV has higher priority than DRC at any stage. DRVs are the factors that characterize the design - standard-cell, macro and physical-cell