Chapter 7 Setup, Hold & Timing Basics

Setup and Hold Time Setup time is the minimum time data must be stable before the active clock edge. Hold time is the minimum time data must remain stable after the active clock edge. KEY Setup = data stable before the clock edge, Hold = data stable after the clock edge.

Setup Check at Placement Yes, setup is checked at placement. Hold is not, because the clock is still ideal at this stage. KEY Setup yes, hold no - clock is ideal at placement.

Fixing Setup and Hold Violations Setup fixes:

• Upsize cells.
• Replace a buffer with two inverters.
• Swap HVT cells for LVT.
• Split long nets and insert buffers.
• Pin swapping.
• Use useful skew - pull the launch clock, push the capture clock.
• Cell cloning. Hold fixes:
• Insert buffers/delay cells.
• Downsize cells.
• Swap LVT cells for HVT.
• Push the launch clock and pull the capture clock. KEY Setup: upsize, LVT swap, buffer long nets, useful skew. Hold: add delay, downsize, HVT swap.