Setup at Max Corner, Hold at Min Corner Setup fails when data arrives late, so it is most pessimistic when delays are largest - hence setup is checked at the max (slow) corner. Hold fails when data arrives too early, so it is most pessimistic when delays are smallest - hence hold is checked at the min (fast) corner. KEY Setup is worst with max delay; hold is worst with min delay.

Setup and Hold on the Same Endpoints Yes - it can happen when the start and end points are connected by different combinational paths. KEY Yes, if different combinational paths run between the same endpoints.

Setup and Hold Fixes - Placement vs CTS Setup fixes during placement:

• Timing path groups - group paths/endpoints so the optimizer can target a chosen set even if larger violations exist elsewhere (ICC: group_path).
• Create bounds - constrain placement of cells with soft/hard, rectangular or rectilinear move bounds (ICC: create_bounds).
• Re-run place_opt with timing-driven mode and high effort so critical-path cells are pulled closer together.
• Adjust the floorplan - macro placement, macro spacing and pin orientation - for better timing. Setup fixes during CTS:
• Increase drive strength of data-path gates - lower output resistance gives a smaller RC delay.
• Use lower-Vt cells (HVT swap to RVT/LVT) to speed up the path.
• Insert buffers on long nets to cut transition and wire delay.
• Reduce excess buffering when wire-delay savings beat the cell-delay cost.
• Route on higher metal layers.
• Replace a buffer with two inverters to sharpen transitions.
• Apply useful (positive) skew - intentionally add delay in the clock